As semiconductor devices become more highly integrated, various techniques for forming LDD-type source/drain regions are widely used in order to improve reliability of MOS transistors. In these techniques, it is required to form a gate spacer on sidewalls of the gate electrodes in order to form the LDD-type source/drain regions. In addition, a self-aligned contact technology has been developed in order to increase the integration density of the semiconductor device. Accordingly, a silicon nitride layer is widely used as a material layer for forming the gate spacer. This is because the gate spacer should have an etching selectivity with respect to an interlayer insulating layer comprising a silicon oxide layer.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method of fabricating a semiconductor device.
Referring to FIG. 1, an isolation layer 2 is formed at a predetermined region of a semiconductor substrate 1 to define an active region. After formation of a gate insulating layer 3 on the active region, a gate electrode layer and a capping layer are sequentially formed on an entire surface of the substrate including the gate insulating layer 3. The capping layer and the gate electrode layer are successively patterned to form a pair of gate patterns 8 that cross over the gate insulating layer 3. Incidentally, the gate insulating layer 3 may be over-etched. Thus, the active region can be exposed. Each of the gate patterns 8 comprises a gate electrode 5 and a capping layer pattern 7, which are sequentially stacked.
Impurity ions are implanted into the active region at a dose of 1×1012 to 1×1014 atoms/cm2 using the gate patterns 8 as ion implantation masks, thereby forming relatively low-concentration source/drain regions 9 at the active region. A gate spacer 11, which is composed of a silicon nitride layer, is then formed on the sidewalls of the gate patterns 8. Using the gate spacer 11 and the gate patterns 8 as ion implantation masks, impurity ions are implanted into the low concentration source/drain regions 9 at a dose of 1×1015 to 5×1015 atoms/cm2 to form relatively high-concentration source/drain regions 13. The relatively low-concentration source/drain region 9 and the relatively high-concentration source/drain region 13 constitute an LDD-type source/drain region 15.
Referring to FIG. 2, an etch stop layer 17 is formed on an entire surface of the substrate having the LDD-type source/drain region 15. The etch stop layer 17 is formed of a silicon nitride layer having an etch selectivity with respect to a silicon oxide layer. Thus, a width W1 of a region, surrounded by the etch stop layer 17 between the adjacent gate patterns 8 is remarkably reduced as compared to the space between the gate patterns 8. This is due to the presence of the gate spacer 11 and the etch stop layer 17. As a result, the aspect ratio of the region, which is surrounded by the etch stop layer 17, is increased. An interlayer insulating layer 19 is then formed on the entire surface of the substrate including the etch stop layer 17. At this time, a void 21 might be formed in the interlayer insulating layer 19 between the adjacent gate patterns 8. This is because the region surrounded by the etch stop layer 17 has a high aspect ratio. Such a void 21 degrades the reliability of the semiconductor device.
Referring to FIG. 3, the interlayer insulating layer 19 and the etch stop layer 17 are successively patterned to form a first contact hole 23a and a second contact hole 23b concurrently. The first contact hole 23a exposes the LDD-type source/drain region 15 between the gate patterns 8 and the second contact hole 23b exposes the LDD-type source/drain region 15 adjacent the isolation layer 2. The etch stop layer 17 prevents the isolation layer 2 from being recessed. It is difficult to maximize the surface area of the LDD-type source/drain regions 15, which are exposed by the first and second contact holes 23a and 23b, due to the gate spacer 11. In particular, in the event that mis-alignment occurs during the photolithography process for forming the first and second contact holes 23a and 23b as shown in FIG. 3, the surface area of the LDD-type source/drain region 15 exposed by the first contact hole 23a is reduced.
According to the conventional technique as described above, it is difficult to maximize the surface area of the LDD-type source/drain region exposed by the contact hole. This is due to the gate spacer, which is formed of a silicon nitride layer. Accordingly, it is difficult to reduce contact resistance in the semiconductor device. In addition, a void may be formed in the interlayer insulating layer due to the gate spacer. Such a void may lead to reliability degradation of the semiconductor device.